1. Field of the Invention
This invention relates to multi-bit-per-cell memory and to read and write processes for multi-bit-per-cell memory
2. Description of Related Art
Conventional non-volatile memory such as a flash memory has memory cells that include floating gate transistors. Each floating gate transistor stores data as charge trapped on an isolated floating gate. The trapped charge in a floating gate transistor determines the threshold voltage of the floating gate transistor, and thus data can be written in or read from a memory cell by setting or determining the threshold voltage of the floating gate transistor in the memory cell. If the methods for setting and determining the threshold voltages are sufficiently accurate and dependable, multiple bits of data can be stored in each memory cell.
One difficulty encountered when attempting to set or determine a threshold voltage with the accuracy required for multi-bit-per-cell storage is variations in operating parameters such as the temperature and supply voltage of the memory. If the operating parameters of the memory during a read differ from the operating parameters when the data was written, the threshold voltage read from a memory cell can differ from the threshold voltage as written. Accordingly, a multi-bit-per-cell memory must account for the variations in operating parameters to avoid data errors. Additionally, charge leakage from the floating gate, memory cell disturb, and endurance history (i.e., the number of write and erase cycles for a memory cell) affect a memory cell's characteristics and can change the threshold voltage of the memory cell. One conventional way to account for variations in operating parameters, charge leakage, and endurance history is to use for each data value, a band of threshold voltages that is sufficiently wide to cover the anticipated variations in the threshold voltages read. However, since the full usable range of threshold voltages of a memory cell is limited, having wide bands for each data value reduces the number of bits that can be stored per memory cell. Accordingly, a multi-bit-per-cell memory is sought that accurately accounts or compensates for variations in operating parameters and reliably provides a maximum number of bits per memory cell.